Clock signal generator
US7595673B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2008 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Aug 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter arranged to generate an inverse of the output signal and a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.