Patent · US Active

Correcting offset errors associated with a sub-ADC in pipeline analog to digital converters

US7595744B2 · kind B2 · utility

7Cited by

5References

11Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Nitin Agarwal · Bengaluru, IN
Ramesh Kumar Singh · Newark, US
Visvesvaraya Pentakota · Bengaluru, IN
Dantes John · Munich, DE
Supreet Joshi · Bengaluru, IN

Key dates

Filing date	Nov 27, 2007
Grant date	Sep 29, 2009
Priority date	—
Expiry date	Nov 27, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03M1/362
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.