Memory device employing three-level cells and related methods of managing
US7596023B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
Inventors
Key dates
| Filing date | Nov 2, 2007 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Dec 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.