Digital interface decode receiver apparatus
US7596188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2004 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Mar 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/63
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A power-down determination circuit calculates the horizontal frequency and vertical frequency, respectively, employing a clock signal obtained from a multiplier circuit and horizontal synchronization signal and vertical synchronization signal obtained from a TMDS decode circuit. The power-down determination circuit then determines whether an input digital signal does or does not have a decodable video format by comparing the calculated horizontal frequency and vertical frequency with horizontal frequencies and vertical frequencies stored beforehand, for output of a power-down control signal indicative of the determination. Thus, in the case where the input digital signal does not have a decodable format, the power-down control signal controls a video/audio processing circuit to enter a power-down mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.