Selective storage of data in levels of a cache memory
US7596662B2 · kind B2 · utility
14Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2006 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | May 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for incrementing a counter value associated with a cache line if the cache line is inserted into a first level cache, and storing the cache line into a second level cache coupled to the first level cache or a third level cache coupled to the second level cache based on the counter value, after eviction from the first level cache. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.