Methodology and system for setup/hold time characterization of analog IP
US7596772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2006 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Sep 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.