Patent · US Active

Semiconductor chip having a soldering layer sequence, and process for soldering a semiconductor chip

US7598529B2 · kind B2 · utility

7Cited by

4References

29Claims

0Family size

Assignee

OSRAM Opto Semiconductors GmbH · DE

Inventors

Andreas Ploessl · Regensburg, DE
Stefan Illek · Donaustauf, DE
Vincent Grolier · Birkenfeld, DE

Key dates

Filing date	Mar 30, 2006
Grant date	Oct 6, 2009
Priority date	—
Expiry date	Oct 21, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH10H20/857
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor chip (1), to which a layer sequence (2) intended for the production of a soldered connection has been applied. The layer sequence (2) comprises a solder layer (15) and an oxidation prevention layer (17), which follows the solder layer (15) as seen from the semiconductor chip (1). A barrier layer (16) is included between the solder layer (15) and the oxidation prevention layer (17). This prevents a constituent of the solder layer (15) from diffusing through the oxidation prevention layer (17) prior to the soldering operation, where it would effect oxidation that is disadvantageous for producing a soldered connection.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.