Semiconductor device comprising transistor pair isolated by trench isolation
US7598541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Sep 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/745
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has transistors (P1,P10,P11) formed in an active region (22) isolated by a trench isolation region, and a predetermined circuit including a first and second transistors (P10,P11) that require symmetry or relativity characteristics, wherein the distances (S1) between a gate electrode and one end of the active region on a source side viewed from the gate electrode in the first and second transistor are substantially same, and the distances (D1) between a gate electrode and one end of the active region on a drain side viewed from the gate electrode in the first and second transistor are substantially same. The predetermined circuit includes, for example, a current mirror circuit that has a transistor pair of which gate is commonly connected, and a differential circuit that has a transistor pair whose sources are commonly connected, where an input signal is supplied to the gate, and an output signal is generated in the drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.