Wafer-scale microcolumn array using low temperature co-fired ceramic substrate
US7598594B2 · kind B2 · utility
1Cited by
9References
11Claims
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Key dates
| Filing date | Oct 24, 2005 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Jan 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/1518
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Provided is a wafer-scale microcolumn array using a low temperature co-fired ceramic (LTCC) substrate. The microcolumn array includes a LTCC substrate having wirings and wafer-scale beam deflector arrays, which are attached to at least one side of the LTCC substrate and has an array of deflection devices deflecting electron beams. The wafer-scale microcolumn array using the LTCC substrate makes it possible to significantly increase the throughput of semiconductor wafers, simplify its manufacturing process, and lower its production cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.