Patent · US Active

Clock synthesis using polyphase numerically controlled oscillator

US7598790B1 · kind B1 · utility

2Cited by

5References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Benjamin Esposito · Oviedo, US
Hong Shan Neoh · Redwood City, US

Key dates

Filing date	Jan 30, 2008
Grant date	Oct 6, 2009
Priority date	—
Expiry date	Apr 4, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output signals represents a different phase of a periodic waveform signal. The extraction circuit extracts a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits. The clock signal generation circuit converts the most significant bits into a serial bit stream that serves as an output clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.