Well bias architecture for integrated circuit device
US7598794B1 · kind B1 · utility
6Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2007 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Mar 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a high voltage switch circuit that can include a first well bias switch configured to track the greater of an input voltage and a supply voltage, a voltage comparator configurable to compare the input voltage to a predetermined reference voltage, and a second well bias switch having a control input coupled to an output of the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.