Patent · US Active

Phase lock loop circuit with delaying phase frequency comparson output signals

US7598816B2 · kind B2 · utility

2Cited by

1References

14Claims

0Family size

Assignee

STMICROELECTRONICS, INC. · US

Inventors

Nitin Agarwal · Bengaluru, IN
Kallol Chatterjee · Noida, IN

Key dates

Filing date	Dec 12, 2006
Grant date	Oct 6, 2009
Priority date	—
Expiry date	Apr 5, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/093
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A phase locked loop (PLL) circuit includes circuitry for preventing an erroneous condition in charge pump operation. The PLL circuit is modified by adding delay elements for connection between the phase frequency detector and the charge pump. A digital logic circuit is also included to provide the clock signals for the loop filter wherein the clock signals have rising edges corresponding to an earlier occurring rising edge of either of the output signals from the phase-frequency detector.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.