Methods and apparatus of stacking DRAMs
US7599205B2 · kind B2 · utility
95Cited by
297References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2008 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Mar 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.