Floating gate memory device with improved reference current generation
US7599221B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2008 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Mar 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device is provided with: a first memory cell including a floating gate transistor; a first bitline connected to a diffusion layer which is used as a source of the first memory cell; a second bitline connected to a diffusion layer which is used as a drain of the first memory cell; a first reference cell including a floating gate transistor; a third bitline electrically isolated from the first bitline and connected to a diffusion layer which is used as a source of the first reference cell; a read circuit identifying data stored in the first memory cell in response to a memory cell signal received from the first memory cell through the second bitline and a reference signal received from the first reference cell through the fourth bitline; and a bitline level controller controlling a voltage level of the third bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.