Wire-speed packet management in a multi-pipeline network processor
US7599361B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2004 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Dec 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5685
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A flow-identification content addressable memory (FICAM) comprising a row of content addressable memory (CAM) cells operable to store a first flow-identification. The first flow-identification corresponds to a first packet dispatched for processing by a pipeline unit (PU) belonging to a network processor. A comparison unit compares a second flow-identification corresponding to a second packet with contents of said at least a row of CAM cells. The comparison unit is further capable of determining if the second flow-identification is same as the first flow-identification. A flow identification eraser is provided for removing the first flow-identification from said at least a row of CAM cells upon determination by the comparison unit that the second flow-identification is same as the first flow-identification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.