Efficient hardware square-root operation
US7599980B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 8, 2005 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Nov 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5525
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that uses the Newton-Raphson technique to compute a square-root. During operation, the system receives a radicand b. Next, the system calculates the square root of b, √{square root over (b)}, by first using the Newton-Raphson technique to find 1/√{square root over (b)}, and then multiplying 1/√{square root over (b)} by b to produce √{square root over (b)}. While using the Newton-Raphson technique to find 1/√{square root over (b)}, the system first obtains an initial estimate x0 for 1/√{square root over (b)} and then iteratively solves the equationEach iteration involves: (1) using a multiplier circuit twice to compute bxi2; (2) performing a bit-wise complement operation on bxi2, shifting the result, and modifying the first two bits of the result to computewhereby an additional pass through an adder circuit or a multiply/add circuit is not required to perform the subtraction operation; and finally (3) using the multiplier circuit to multiply xi byto compute
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.