Message handling communication between a source processor core and destination processor cores
US7599998B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2004 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Feb 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus comprises at least one source processor core, at least two destination processor cores, a message handler and a bus arrangement providing a data communication path between the source core, the destination cores and the message handler. The message handler has plurality of message-handling modules. At least one of the message-handling modules has a message receipt indicator that is modifiable by each of the destination processor cores to indicate that a message has been received at its destination. This message-handling module also has a transmission completion detector operable to detect, in dependence upon a message receipt indicator value that a message has been received by all of the at least two destination processor cores and to initiate transmission of an acknowledgement signal to the source processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.