Method and apparatus for variable delay data transfer
US7600143B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 2004 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Jul 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus allows data to traverse a cache interface device in one of four transfer modes. A fast bypass mode provides received cache data within the same master clock cycle as it was received, whereas a slow bypass mode provides received cache data within the subsequent master clock cycle. A queue mode provides a programmable amount of delay to be used by the cache interface device, whereby consecutive queue mode provides a First In First Out (FIFO) operation to consecutively retrieve queued data. A block queue mode, on the other hand, provides a method to retrieve queued data using a programmable offset so as to enable partial cache line retrieval without the need to use No Operation (NoP) clock cycles on the cache interface data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.