Method of verifying integrity of control module arithmetic logic unit (ALU)
US7600161B2 · kind B2 · utility
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14References
32Claims
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Key dates
| Filing date | Aug 13, 2004 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Feb 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of verifying the integrity of an arithmetic logic unit (ALU) of a control module includes inputting a first test value into one of a plurality of registers of the ALU and inputting a second test value into remaining registers of the plurality of registers. A first set of operations is performed between the one of the plurality of registers and each of the remaining registers to produce a first set of results. A fault is indicated when one of the first set of results varies from a first predetermined result.
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