Convolutional interleaver and deinterleaver
US7600163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2003 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Mar 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for receiving and storing an incoming sequence and for forwarding the bytes of the incoming sequence as an outgoing sequence in a different byte order includes a cache memory and a main memory for storing bytes of the incoming sequence until they can be forwarded as bytes of the outgoing sequence. A control circuit selectively burst mode writes sequences of incoming bytes that need be stored for a relatively long time to blocks of sequential addresses of the main memory, writes individual bytes of the incoming sequence that need be stored for a relatively short time to selected addresses of the cache memory, and reads bytes out of the cache memory and the main memory when needed to form the outgoing sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.