Techniques for providing a failures in time (FIT) rate for a product design process
US7600202B1 · kind B1 · utility
2Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2006 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Dec 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for providing a product FIT rate is performed within electronic circuitry (e.g., one or more computerized devices). The technique involves receiving a Mean Time To Failure (MTTF) target for a product and a Mean Time To Repair (MTTR) target for the product (e.g., a circuit board module). The technique further involves establishing a FIT rate based on the MTTF target and the MTTR target, and then outputting the FIT rate to a design process for the product (e.g., a circuit board design process). The FIT rate is a number of product failures expected per amount of time of product operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.