Semiconductor array and method for manufacturing a semiconductor array
US7601584B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 2005 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Nov 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/177
Abstract
A method for manufacturing a semiconductor array, particularly a high-frequency bipolar transistor, is provided, the method includes process steps, so that a dielectric is produced on a mono-crystalline, first semiconductor region of a first conductivity type, a silicide layer is deposited and patterned in such a way that the silicide layer is insulated from the first semiconductor region by the dielectric, and, to form a base region, a second semiconductor region of a second conductivity type is applied to the first semiconductor region and to the silicide layer in such a way that the second semiconductor region lies with a first interface on the first semiconductor region and with a second interface on the silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.