Method of forming fine patterns in semiconductor device and method of forming gate using the same
US7601622B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Dec 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There are provided a method of forming fine patterns in a semiconductor device, and a method of forming a gate with a fine critical dimension using the same. In the method of forming fine patterns in a semiconductor device, a plurality of sidewall buffer patterns are formed on a gate insulating layer formed on a substrate, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. A sidewall layer is deposited on the sidewall buffer patterns as well as the gate insulating layer. The sidewall layer is etched such that sidewall patterns remain on sidewalls of the sidewall buffer patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.