On-chip structure for electrostatic discharge (ESD) protection
US7601991B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 26, 2007 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Sep 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/251
Abstract
A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structureare n-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.