Common mode noise reduction using parasitic capacitance cancellation
US7602159B2 · kind B2 · utility
9Cited by
10References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 26, 2007 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Sep 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B15/02
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A negative capacitance is developed by configuring an inductor as two inversely or opposingly coupled windings having different numbers of turns and connecting a capacitance to a center tap between the two windings. The negative capacitance is developed on the side of the inductor having the winding with the greater number of turns. The negative capacitance so developed may advantageously be used to cancel any capacitance or parasitic capacitance desired for reducing power loss, increasing switching speed or reducing or eliminating common mode noise in a switched circuit such as a switched power converter
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.