Input cancellation circuit
US7602169B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2008 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45682
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein both paths substantially match in resistance. In another embodiment, a differential signal is substantially cancelled by a pseudo differential arrangement including two independent input resistance paths each in parallel with a corresponding negative resistance path, wherein the resistance paths substantially match the input resistance paths. In yet another embodiment, a differential signal is substantially cancelled by a differential arrangement including two resistance paths wherein a first negative resistance path is coupled between the first differential input and the second differential output and the second negative resistance path is coupled between the second input and the first output. In yet another embodiment, a current controlled current source may provide the negative amplification for the negative resistance path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.