Using programmable latch to implement logic
US7602213B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 2007 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Jan 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1733
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. The circuit includes a logic block comprising a plurality of logic inputs and at least one logic output, the logic output generating a logic function of the plurality of logic inputs; a first latch input to provide a data state to store in the latch is coupled to said at least one output of logic block; a global latch input to change the stored data state of the latch couple by a programmable method to a local input; and a latch output, wherein when the local input is coupled to the global latch input, the latch output generates logic function of the logic output and the local input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.