Charge-pump circuit
US7602231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2006 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Oct 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/07
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.