Method of making a non-volatile memory (NVM) cell structure and program biasing techniques for the NVM cell structure
US7602641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2008 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Sep 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of making a non-volatile memory (NVM) cell structure includes the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell. A second equalize structure is connected between the second pass gate structure and the second NVM cell, the second equalize structure being responsive to a second equalize signal to connect the second NVM cell to ground. Appropriate biasing condition…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.