Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration
US7603540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2008 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Jul 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.