Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry
US7603639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2007 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Sep 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive to their time domain variations at respective frequencies. A simulated, substantially noise-only, clock tree output signal is generated in a frequency domain, wherein some components are removed responsive to at least one clock signal frequency and scaled magnitudes of the components. A second simulated clock circuitry output signal is generated responsive to a transfer function of certain clock circuitry. A circuit structure or fabricating process is selected responsive to jitter of the second simulated clock circuitry output signal. The IC may be fabricated using the selected process and may include the selected structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.