Placer with wires for RF and analog design
US7603642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Jan 17, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.