Integrated circuit routing and compaction
US7603644B2 · kind B2 · utility
15Cited by
68References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2006 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Mar 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing is used for nets than span more than one row or channel. Alter the space between rows, larger or smaller, which will allow routing of the nets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.