Method for the integration of two bipolar transistors in a semiconductor body, semiconductor arrangement in a semiconductor body, and cascode circuit
US7605047B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2006 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | May 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
A method for the integration of two bipolar transistors in a semiconductor body, wherein, for the first bipolar transistor, a first emitter semiconductor region, a first base semiconductor region, and a first collector semiconductor region are produced. A recombination layer is applied to the first bipolar transistor, which is adjacent to the first emitter semiconductor region or the first collector semiconductor region and is constructed in such a way that charge carriers recombine on the recombination layer, and next, the second bipolar transistor is placed on the recombination layer, wherein a second emitter semiconductor region, a second base semiconductor region, and a second collector semiconductor region are produced on the recombination layer, so that the second emitter semiconductor region or the second collector semiconductor region is adjacent to the recombination layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.