Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components
US7605066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2006 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Jun 28, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/762
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method realizes an electric connection between a nanometric circuit and standard electronic components. The method includes: providing, above a semiconductor substrate, a seed having a notched wall substantially perpendicular to the substrate, the wall having n recesses spaced apart from one another; and realizing n conductive nanowires alternated with insulating nanowires. Each realization of a conductive nanowire fills a corresponding recess by a respective elbow-like portion of the conductive nanowire, and partially fills the other recesses by respective notched profile portions, thereby forming the nanometric circuit. The method forms, above the nanometric circuit, an insulating layer; opens, in the insulating layer, n windows respectively corresponding with the recesses, thereby exposing the respective elbow-like portions; and realizes, above the insulating layer, n conductive dies addressed towards the standard electronic components and respectively overlapping the windows, thereby forming n contacts realizing the electric connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.