Device, system and method of delay calibration
US7605625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2007 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Mar 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.