Digitally corrected SAR converter including a correction DAC
US7605741B2 · kind B2 · utility
20Cited by
11References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2006 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Dec 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog to digital converter having improved differential non-linearity is provided. The converter has a memory which is used to look up the actual weight or a weight error corresponding to the bits that have been kept as part of the SAR process to form an output correction value A part of this, for example a residue (the part following the decimal point in a decimal representation) is used to drive a correction DAC which causes a correction to be applied to the trial value presented to a comparator used by the ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.