Access collision within a multiport memory
US7606108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2007 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Apr 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.