Distributed packet processing architecture for network access servers
US7606245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2005 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Sep 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/583
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An access server architecture, and methods for use of the architecture, are disclosed. The architecture and methods are designed to increase the scalability of and balance processor load for a network access server device. In this architecture, packet forwarding and packet processing are distributed amongst the cards serving the low-speed access lines, such that each line card is responsible for performing forwarding and packet processing for packets associated with the low-speed ports that line card serves. As the number of line cards expands, forwarding resources are expanded in at least rough proportion. The NAS route switch controller, and the high-speed ports, are largely relieved of packet processing tasks because the egress port uses a distribution engine that performs a cursory examination on one or more header fields on packets received—comprehending only enough information to allow each packet to be distributed to the appropriate line card for full packet processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.