Sub-sequence accumulation filter and method
US7606292B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2005 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Feb 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70707
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A parallel correlator and method includes temporarily storing in a series of P sequence registers, each of length R1, serial bit-sequences of a code of length N=P*R1. In a first-level of processing, certain unique bit sequences are inverted to reduce the number of unique bit sequences by half. Identical bit-sequences are then combined and temporarily stored in a first-level sub-accumulation register. Alternatively, bit sequences differing by only one bit may be combined in a common first-level sub-accumulation register. Further levels of similar processing may be imposed, where each subsequent level taps and inverts only a portion of the bits in the above level of processing, thereby reducing the number of unique bit sequences. Finally, all negative energy is combined in one register position, inverted, and added to all positive energy in the other register positions. When the spreading code was aligned among the series of sequence registers, the energy is added coherently and an energy peak is output, indicating alignment of the spreading code in the sequence registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.