Variable signal delaying circuit, quadrature frequency converter and radio frequency tuner
US7606332B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2006 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Feb 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D7/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator. A pulse stream generating arrangement produces pulse streams of different pulse widths and pulse control logic controls a selector for selecting any one of the pulse streams. In a first mode of operation, the control logic monitors the charge pump/filter output and selects the pulse stream which minimizes change in the output. The selection is fixed and the output of the charge pump/filter is then supplied as a correction signal to the control input of the analog delay line. Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.