Single wire bus for connecting devices and methods of operating the same
US7606955B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2004 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Nov 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4295
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A master/slave system architecture that includes a single wire bus, a master device and bus interface coupled to the bus. The system further includes plurality of slave devices having respective bus interfaces coupled to the bus. Each of the slave devices having a designated device identification. There is further provided a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions composed each of bit signals that belong each to a bit signal type from among a plurality of bit signal types. Each bit signal type has a time interval that is discernible from respective time intervals of all other bit signal types from among the plurality of bit signal types.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.