Method and apparatus for block and rate independent decoding of LDPC codes
US7607065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2005 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Dec 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6516
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of the plurality of sub-matrices has a single entry. Each of the sub-matrices has at least one associated Phi-node, wherein each Phi-node comprises a memory device having a plurality of memory elements, wherein one or more of the memory elements may be selectively disabled. The Phi-nodes may be selectively disabled, for example, at run-time. The Phi-node optionally further comprises a multiplexer in order to provide a variable parity check matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.