Patent · US Active

System, method and computer program product for timing-independent sequential equivalence verification

US7607115B1 · kind B1 · utility

5Cited by

5References

17Claims

0Family size

Assignee

Calypto Design Systems, Inc. · US

Inventors

Venkatram Krishnaswamy · Los Altos, US
Shusaku Yamamoto · San Jose, US
Junichi Tatsuda · Tokyo, JP

Key dates

Filing date	Oct 4, 2006
Grant date	Oct 20, 2009
Priority date	—
Expiry date	Jun 12, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system, method and computer program product are provided for verifying sequential equivalence. In use, input is fed to a first system and a second system in a timing-independent manner to generate output. To this end, sequential equivalence of the first system and the second system may be verified, based on the output.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.