Passivated tiered gate structure transistor and fabrication method
US7608497B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Apr 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A method for fabricating a tiered structure includes forming a gate on a semiconductor substrate. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped and a passivation layer is formed over the gate foot and the substrate. A gate head mask is formed over the gate foot with the gate head mask exposing a portion of the passivation layer on a top portion of the gate foot. The portion of the passivation layer on the top portion of the gate foot is removed to expose the top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.