Deterministic generation of an integrated circuit identification number
US7608932B2 · kind B2 · utility
2Cited by
6References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 23, 2005 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Sep 23, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of the chip, the first sections being individually connected, by at least one of their ends, to the chip, and exhibiting different lengths, the position of the cutting line with respect to the chip edge conditioning the identification number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.