Filterless class-D speaker driver with less switching
US7609110B2 · kind B2 · utility
1Cited by
1References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Oct 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods for designing a filterless class-D amplifier and driver are described herein. In the exemplary embodiment, a feedback loop is used to stabilize the filterless class-D amplifier. A pulse width modulated (PWM) output signal is generated by adding a comparator input signal to a comparative signal, and comparing the sum to a peak voltage, which can be a peak value of the comparative signal. A limit of one PWM sample will be generated half per period of the comparative signal, resulting in lower dynamic switching noise and a decreased sensitivity to jitter noise than conventional filterless class-D amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.