Circuit, system, and method for multiplexing signals with reduced jitter
US7609799B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 2006 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Apr 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.