Configuring flash memory
US7610528B2 · kind B2 · utility
3Cited by
14References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2006 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Jan 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure, or cycle, a flash memory using a serial interface and test other functional units using the same serial interface substantially concurrently with cycling the flash memory. In some implementations, cycling the flash memory includes erasing and writing to the flash memory in specific patterns in order to dissipate charge that may have accumulated during a fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.