Method and system for simulating state retention of an RTL design
US7610571B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2006 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Nov 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.